Mentor’s analog/mixed-signal verification tools offer a language-neutral verification environment for complex analog/mixed-signal System-on-Chip designs. Questa ADMS combines four high performance simulation engines in one efficient tool: Eldo Classic for general purpose analog simulations, Questa for digital simulations, ADiT™ for fast transistor-level simulations and Eldo RFfor radio frequency simulations. Additionally, Mentor’s recently released Faster-SPICE solution, Eldo Premier, providing increased performance and capacity, especially for very large circuits, without sacrificing accuracy. These technologies enable top-down design and bottom-up verification of multi-million gate AMS SoC designs.
AFS is the fastest digital and mixed design verification platform in nanometer IC designs. Currently, many companies have been using AFS tools to verify their designs that require large area and high speed (i.e. high-speed I/O, PLL, ADC/DAC, CMOS image sensor, RFIC and embedded memory etc…)
Mentor Graphics IC implementation solutions, Olympus-SoC™ and Calibre® InRoute, deliver innovative technologies to solve the power, performance, capacity, time-to-market, and variability challenges encountered at the leading-edge process nodes.
Mentor’s new Pyxis Custom IC Design Platform includes integrated solutions for design capture (Pyxis Schematic), floorplanning(Pyxis Implement), custom routing, polygon editing(Pyxis Layout), physical layout, schematic-driven layout, concurrent editing and chip assembly. To help companies jump-start their design cycles and cut time-to-market, Mentor Graphics and its foundry partners have developed design kits.
Tanner AMS IC design flow integrates the whole analog/mixed-signal design flow. Analog digital simultaneous simulation, synthesis including design-for-test, place and routing, timing analysis are all possible to perform in an integrated environment with lower costs.
It is possible to implement 3D MEMS design and fabrication and integrate with analog/mixed signal processing designs in a single IC. Foundry-supported applications like mechanical, thermal, acoustic, electrical, electrostatic, magnetic and flow analysis are provided for MEMS designs. This in turn, enables high manufacturability in MEMS designs.
Mentor’s IC verification and sign-off includes not only traditional rule-based physical verification and parasitic extraction, but also new capabilities and automated technologies that help improve yield by enhancing the design itself with the following products: Calibre nmDRC, Calibre nmLVS
Calibre® LFD™ (Litho Friendly Design) is the first production-proven EDA tool to address the urgent issue of how to manage lithographic process variability in the early stages of design creation. Calibre LFD accurately models the impact of lithographic processes on “as-drawn” layout data to determine the actual “as-built” dimensions of fabricated gates and metal interconnects with the following products: Calibre LFD™, Calibre YieldAnalyzer, Calibre YieldEnhancer
Mentor Graphics offers the most comprehensive IC design, verification, DFM and test technologies available today with the following products: ADiT Rail, Calibre Automatic Waivers, Calibre CMPAnalyzer, Calibre DESIGNrev™, Calibre Interactive™, Calibre Pattern Matching, Calibre PERC,Calibre RealTime, Calibre RVE™, Calibre xACT 3D, Calibre xL, Calibre xRC, EZwave, Eldo Premier,Questa ADMS RF
Low k1 photolithography processes are driving up the complexity and data volume of RET applications in nanometer designs. At 45nm and beyond, more complex models and through-process-window correction and verification requirements significantly increase computational burden. Both the lithographic challenges and the computational complexity associated with the advanced process nodes create a need for advanced capabilities in computational lithography software and hardware. Additional functionalities are supported with the following products: Calibre OPCverify™,Calibre nmOPC, Calibre OPCpro™, Calibre OPCsbar™, Calibre WORKbench™
The next few IC technology nodes will be more challenging than any other transition since the first integrated circuit. Until the 32 nm node, distortions involved in making the masks using 193 nm lithography were small and had little impact since mask features are four times larger than the actual features on a die. Traditional OPC has mainly addressed the wafer image transfer and only included mask making effects as a part of the overall OPC model. Additional functionalities are supported with the following products: Calibre MPCpro, Calibre nmMPC
Mentor’s Mask Data Preparation (MDP) solution is fully compatible with the Calibre platform, enabling you to complete all resolution enhancement processing and mask data format conversion tasks in one mask fabrication batch run using a single control language. Additional functionalities are supported with the following products: Calibre FRACTURE™, Calibre MDPmerge™, Calibre MDPverify™, Calibre MDPview™, Calibre® MAPI™, Calibre® MASKOPT™
Advanced design techniques are used in creating the logic portions of SoCs, presenting significant challenges to achieving high-quality silicon test. To meet these challenges, Mentor Graphics offers the industry’s most powerful suite of logic test solutions with the following products: Tessent BoundaryScan, Tessent FastScan, Tessent LogicBIST, Tessent PLLTest, Tessent SoCScan,Tessent TestKompress
Tessent® memory test solutions provide the industry’s most advanced memory self-test and repair capabilities with the following products: Tessent BoundaryScan, Tessent MemoryBIST
The Tessent™ mixed-signal test solutions are vendor- and ATE-independent, addressing the growing number of SerDes interfaces and PLLs on today’s SoC designs. Characterization with PC plus GPIB-controlled benchtop equipment reduces tester hardware requirements, and the microWire-controlled clock conditioner PLL shortens your time-to-market. Tessent SerdesTest and Tessent PLLTest minimize tester hardware requirements and reduce tests costs.
The Tessent® silicon learning products increase productivity during critical silicon validation and yield ramp phases. The products provide solutions for test bring-up, silicon characterization, diagnosis-driven yield analysis, and failure analysis. Combining statistical analysis and scan diagnosis has been shown to reduce time to root cause of yield loss with the following products:Tessent Diagnosis, Tessent SiliconInsight, Tessent YieldInsight